ASIC Design Verification, Technical Lead - 22010132

  Location: United States
  Full-Time

Job Title:      ASIC Design Verification, Technical Lead                

Department: R&D  

Region:         Sunnyvale, CA                                                              

COMPANY DESCRIPTION:

Quanergy’s (NYSE:  QNGY and QNGY.WS) mission is to create powerful, affordable smart LiDAR solutions for automotive and IoT applications to enhance people’s experiences and safety. Quanergy has developed the only true 100% solid-state CMOS LiDAR sensor built on optical phased array (OPA) technology to enable the mass production of low-cost, highly reliable 3D LiDAR solutions. Through Quanergy’s smart LiDAR solutions, businesses can now leverage real-time, advanced 3D insights to transform their operations in a variety of industries including industrial automation, physical security, smart cities, smart spaces and much more. Quanergy solutions are deployed by nearly 400 customers across the globe. 

JOB DESCRIPTION:

The ASIC Design Verification Technical Lead at Quanergy will be responsible for collaboratively developing and maintaining our UVM-based verification environment.  She/He will be a leader for verification efforts at the module and chip-level for both ASIC and FPGA-based designs.  A successful candidate will have demonstrated experience developing and maintaining a production UVM environment as well as a demonstrated ability to develop scripts and tools for automation.  He/she will work closely with ASIC designers to ensure that the RTL implementations meet all system-level requirements. He/shell will also perform post-silicon chip bring-up and system lab testing tasks during the appropriate design phase.

REQUIRED EXPERIENCE:

• Possesses a strong understanding of the state-of-the-art in verification techniques, including assertion-based and metric-driven verification.
• Expertise in writing a detailed test-plan and building a sophisticated directed and random verification environment.
• Expertise in developing mix-signal modeling, UVM scoreboards, checkers, and monitors.
• Demonstrated experience in transferring directed test benches from designers into constrained random testbenches with requirements-driven assertion-based verification, targeting reset verification, contention checking, clock gating, and clock domain synchronization.
• Demonstrated experience in performing post-silicon bring-up tasks and measurements on engineering samples.
• Ability to automate tasks through scripting and template generation to ensure design uniformity and consistency while improving productivity.
• Proficiency with TCL and comfortable using other scripting languages like Perl or Python.

EDUCATION REQUIRED:

• B.S. degree with 10+years of experience or M.S./Ph.D. degree with 8+ years of experience in Design Verification with at least 2 years of experience with SystemVerilog and UVM.

PREFERRED EXPERIENCE:

• Experience with VerilogA models combined with RTL.
• Experience with formal property checking tools.
• Experience configuring and maintaining EDA tools and computing infrastructure
• Familiarity with DFT/DFx techniques and generic lab measurement equipment for ASIC post-silicon verification.
• Familiarity with automotive design requirements and ISO26262.
• Exposure to the entire ASIC design flow, both front-end design and back-end implementation and physical verification.